Different types of semiconductor packages have been developed recently with a smaller outline, and a higher pin count than conventional plastic or ceramic packages. These semiconductor packages are broadly referred to as BGA packages, chip scale packages or flip chip packages. One particular type of package is referred to as a board-on-chip (BOC) package.
Referring to FIG. 1A, a prior art BOC package 10 is illustrated. The BOC package 10 includes a substrate 12, terminal contacts 14 on the substrate 12, and a semiconductor die 16 attached to the substrate 12 in electrical communication with the terminal contacts 14. Typically the substrate 12 comprises a reinforced polymer laminate material, such as bismaleimide triazine (BT), or a polyimide resin, and the terminal contacts 14 comprise solder balls in a dense area array, such as a ball grid array (BGA). In addition, the substrate 12 includes patterns of metal conductors 24 in electrical communication with the terminal contacts 14. The conductors 24 typically fan out from bond pads 30 on the die 16 to the grid pattern of the terminal contacts 14.
The BOC package 10 also includes adhesive members 26, such as strips of adhesive tape, attaching a circuit side 32 of the die 16 to the substrate 12. The substrate 12 includes a bonding opening 28, and the die 16 is attached to the substrate 12 with the bond pads 30 on the circuit side 32 aligned with the bonding opening 28. In addition, wires 22 are placed through the opening 28, and are wire bonded to the bond pads 30 on the die 16 and to the conductors 24 on the substrate 12. The BOC package 10 also includes a die encapsulant 18 encapsulating the die 16, and a wire bond encapsulant 20 encapsulating the wires 22. The die encapsulant 18 and the wire bond encapsulant 20 typically comprise a plastic material, such as a Novoloc based epoxy, formed using transfer molding process.
As shown in FIG. 1B, the adhesive members 26 do not completely cover the circuit side 32 of the die 16. Accordingly, the die encapsulant 18, and also the wire bond encapsulant 20, can be in physical contact with exposed portions of the circuit side 32 of the die 16.
One problem with the BOC package 10 is that stress defects often develop in the die 16 following the packaging process. As used herein a “stress defect” means the die 16 has an improper circuit structure that produces a present or future electrical failure in the operation of the die 16 or elements thereof.
One type of stress defect 38 is illustrated in FIG. 1C. In this example, the die 16 includes interconnect conductors 34 on the circuit side 32 covered by a die passivation layer 36. The interconnect conductors 34 are in electrical communication with the bond pads 30, and with the integrated circuits (not shown) contained on the die 16. The stress defects 38 can comprise cracks that form in the die passivation layer 36 and in the interconnect conductors 34. These stress defects 38 can cause opens and shorts to occur in the interconnect conductors 34. Stress defects 38 can also occur on other elements on the die 16, such as on the bond pads 30.
It has been theorized that the stress defects 38 are caused by fillers in the die encapsulant 18, or in the wire bond encapsulant 20 that are in physical contact with the circuit side 32 of the die 16. For example, epoxies used for the die encapsulant 18 and the wire bond encapsulant 20 often contain silicates, such as SiO2, that are used to adjust various physical or electrical characteristics of the epoxies. These fillers in physical contact with the circuits side 32 of the die 16 may be one source of stress defects 20.
The present invention is directed to an improved semiconductor package having a stress defect barrier, and to a method for fabricating the package.